Method for forming an asymmetric crystalline structure memory cell
US6927120B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2003 |
| Grant date | Aug 9, 2005 |
| Priority date | — |
| Expiry date | May 27, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/31
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Asymmetrically structured memory cells and a fabrication method are provided. The method comprises: forming a bottom electrode; forming an electrical pulse various resistance (EPVR) first layer having a polycrystalline structure over the bottom electrode; forming an EPVR second layer adjacent the first layer, with a nano-crystalline or amorphous structure; and, forming a top electrode overlying the first and second EPVR layers. EPVR materials include CMR, high temperature super conductor (HTSC), or perovskite metal oxide materials. In one aspect, the EPVR first layer is deposited with a metalorganic spin coat (MOD) process at a temperature in the range between 550 and 700 degrees C. The EPVR second layer is formed at a temperature less than, or equal to the deposition temperature of the first layer. After a step of removing solvents, the MOD deposited EPVR second layer is formed at a temperature less than, or equal to the 550 degrees C.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.