Method for forming a self-aligned buried strap in a vertical memory cell
US6927123B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 2004 |
| Grant date | Aug 9, 2005 |
| Priority date | — |
| Expiry date | May 16, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/0383
Abstract
A method for forming a self-aligned buried strap in a vertical memory cell. A semiconductor substrate with a trench is provided, a capacitor wire is formed on the bottom portion of the trench, and a collar dielectric layer is formed between the capacitor wire and the semiconductor substrate to act as an isolation. The capacitor wire and the collar dielectric layer are etched to a predetermined depth, such that a gap is formed between the spacer and the capacitor wire and the collar dielectric layer. Ions are doped into the exposed semiconductor substrate to form an ion doped area acting as a buried strap. The spacer is removed, and an exposed collar dielectric layer is etched below the level of the surface of the capacitor wire, and a groove is formed between the capacitor wire and the trench sidewall to fill with a conducting layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.