Bitline hard mask spacer flow for memory cell scaling
US6927145B1 · kind B1 · utility
52Cited by
10References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2004 |
| Grant date | Aug 9, 2005 |
| Priority date | — |
| Expiry date | Mar 9, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
The invention is a semiconductor device and a method of forming the semiconductor device. The semiconductor device comprises a substrate; buried bitlines formed in the substrate narrower than achievable at a resolution limit of lithography; a doped region formed adjacent at least one of the buried bitlines; a charge trapping layer disposed over the substrate; and a conductive layer disposed over the charge trapping layer, wherein the doped region adjacent the least one of the buried bitlines inhibits a leakage current between the buried bitlines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.