Low-k dielectric layer stack including an etch indicator layer for use in the dual damascene technique

US6927161B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Hartmut Ruelke · Dresden, DE
• Christof Streck · Coswig, DE
• Georg Sulzer · Dresden, DE

Key dates

• Filing date: Apr 22, 2003
• Grant date: Aug 9, 2005
• Expiry date: Apr 22, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A low-k dielectric layer stack is provided including a silicon based dielectric material with a low permittivity, wherein an intermediate silicon oxide based etch indicator layer is arranged at a depth that represents the depth of a trench to be formed in the dielectric layer stack. A thickness of the etch indicator layer is sufficiently small to not unduly compromise the overall permittivity of the dielectric layer stack. On the other hand, the etch indicator layer provides a prominent optical emission spectrum to reliably determine the time point when the etch process has reached the etch indicator layer. Thus, the depth of trenches in highly sophisticated low-k dielectric layer stacks may reliably be adjusted to minimize resistance variations of the metal lines.