Hartmut Ruelke
32Patents
8h-index
36Co-inventors
71Inventor score
Filing activity: Jan 18, 2000 → Sep 11, 2013
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6599827B1 | Methods of forming capped copper interconnects with improved electromigration resistance | Electricity | 25 | Expired |
| US6797652B1 | Copper damascene with low-k capping layer and improved electromigration reliability | Emerging Cross-Sectional Technologies | 20 | Expired |
| US6506677B1 | Method of forming capped copper interconnects with reduced hillock formation and improved electromigration resistance | Electricity | 18 | Expired |
| US8084088B2 | Method of improving the wafer-to-wafer thickness uniformity of silicon nitride layers | Electricity | 17 | Active |
| US6368948B1 | Method of forming capped copper interconnects with reduced hillocks | Electricity | 13 | Expired |
| US6893956B2 | Barrier layer for a copper metallization layer including a low-k dielectric | Electricity | 12 | Expired |
| US6596631B1 | Method of forming copper interconnect capping layers with improved interface and adhesion | Emerging Cross-Sectional Technologies | 9 | Expired |
| US6720242B2 | Method of forming a substrate contact in a field effect transistor formed over a buried insulator layer | Electricity | 9 | Expired |
| US7022602B2 | Nitrogen-enriched low-k barrier layer for a copper metallization layer | Electricity | 7 | Expired |
| US6235654A | Process for forming PECVD nitride with a very low deposition rate | Electricity | 7 | Expired |
| US6372668B1 | Method of forming silicon oxynitride films | Electricity | 5 | Expired |
| US6927161B2 | Low-k dielectric layer stack including an etch indicator layer for use in the dual damascene technique | Electricity | 4 | Expired |
| US6221793A | Process for forming PECVD undoped oxide with a super low deposition rate on a single state deposition | Electricity | 4 | Expired |
| US7381602B2 | Method of forming a field effect transistor comprising a stressed channel region | Electricity | 4 | Expired |
| US7326646B2 | Nitrogen-free ARC layer and a method of manufacturing the same | Emerging Cross-Sectional Technologies | 3 | Expired |
| US8772178B2 | Technique for forming a dielectric interlayer above a structure including closely spaced lines | Electricity | 3 | Active |
| US6989601B1 | Copper damascene with low-k capping layer and improved electromigration reliability | Emerging Cross-Sectional Technologies | 3 | Expired |
| US8338284B2 | Stress engineering in a contact level of semiconductor devices by stressed conductive layers and an isolation spacer | Electricity | 3 | Active |
| US7341903B2 | Method of forming a field effect transistor having a stressed channel region | Electricity | 2 | Expired |
| US6569768B2 | Surface treatment and capping layer process for producing a copper interface in a semiconductor device | Electricity | 2 | Expired |
| US7030044B2 | Method of forming a cap layer having anti-reflective characteristics on top of a low-k dielectric | Emerging Cross-Sectional Technologies | 2 | Expired |
| US7998882B2 | Particle reduction in PECVD processes for depositing low-k material by using a plasma assisted post-deposition step | Electricity | 1 | Active |
| US7314824B2 | Nitrogen-free ARC/capping layer and method of manufacturing the same | Electricity | 1 | Expired |
| US8741787B2 | Increased density of low-K dielectric materials in semiconductor devices by applying a UV treatment | Electricity | 1 | Active |
| US8211795B2 | Method of forming a dielectric cap layer for a copper metallization by using a hydrogen based thermal-chemical treatment | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.