Semiconductor package exhibiting efficient lead placement
US6927483B1 · kind B1 · utility
69Cited by
156References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2003 |
| Grant date | Aug 9, 2005 |
| Priority date | — |
| Expiry date | Mar 7, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18301
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package exhibiting efficient placement of semiconductor leads in a micro lead frame design is provided. An integrated circuit die is bonded to the top surfaces of leads, thereby allowing the leads to partially reside under the die. As a result, surface area on the bottom surface of the semiconductor package is recaptured. The die can be further bonded a die paddle if so desired. One or more channels can be cut into the bottom surface of the package in order to separate first and second leads. Such channels allow separate leads to be fabricated from a single lead member which is subsequently cut.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.