Method for determining an ESD/latch-up strength of an integrated circuit

US6930501B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Silke Bargstadt-Franke · Birkenfeld, DE
• Kai Esmark · Schwanau, DE
• Harald Gossner · Riemerling, DE
• Philipp Riess · Munich, DE
• Wolfgang Stadler · Hilpoltstein, DE
• Martin Streibl · Petershausen, DE
• Martin Wendel · Höhenkirchen-Siegertsbrunn, DE

Key dates

• Filing date: Jun 14, 2004
• Grant date: Aug 16, 2005
• Expiry date: Jun 14, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/3011
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for determining an ESD/latch-up strength of an integrated circuit includes producing an integrated circuit and a test structure using the same fabrication process. Electrical parameters at the test structure are measured and characteristic values associated with the integrated circuit are derived from the measured parameter values, wherein the characteristic values characterize an ESD or latch-up characteristic curve associated with the integrated circuit. The method further includes testing whether the characteristic values in each case lie within a predetermined range assigned to them, wherein the ranges are chosen such that a desired ESD/latch-up strength is present if the characteristic values in each case lie within their range.