High selectivity and residue free process for metal on thin dielectric gate etch application
US6933243B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2002 |
| Grant date | Aug 23, 2005 |
| Priority date | — |
| Expiry date | Jun 28, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/667
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for etching electrodes formed directly on gate dielectrics are provided. In one aspect, an etch process is provided which includes a main etch step, a soft landing step, and an over etch step. In another aspect, a method is described which includes performing a main etch having good etch rate uniformity and good profile uniformity, performing a soft landing step in which a metal/metal barrier interface can be determined, and performing an over etch step to selectively remove the metal barrier without negatively affecting the dielectric. In another aspect, a method is provided which includes a first non-selective etch chemistry for bulk removal of electrode material, a second intermediate selective etch chemistry with end point capability, and then a selective etch chemistry to stop on the gate dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.