Semiconductor memory with gate at least partially located in recess defined in vertically oriented semiconductor layer
US6933556B2 · kind B2 · utility
58Cited by
13References
46Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Jun 20, 2002 |
| Grant date | Aug 23, 2005 |
| Priority date | — |
| Expiry date | Mar 16, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/30
Abstract
A semiconductor memory comprises: a first conductivity type semiconductor substrate and one or more memory cells each constituted of an island-like semiconductor layer having a recess on a sidewall thereof, a charge storage layer formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, and a control gate formed on the charge storage layer, wherein at least one charge storage layer of said one or more memory cells is partially situated within the recess formed on the sidewall of the island-like semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.