Electromagnetic noise shielding in semiconductor packages using caged interconnect structures
US6933599B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2003 |
| Grant date | Aug 23, 2005 |
| Priority date | — |
| Expiry date | Oct 27, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device has a die (10) overlying and electrically connected to a support structure (11), such as a substrate or a lead frame, via a plurality of interconnects. Aggressor interconnects (32, 38) are noise sources to victim interconnects (29, 59) carrying sensitive signals. An arrangement of shield interconnects (51-58) surround the victim interconnect (29, 59) in a cage-like structure to significantly block noise from the aggressor interconnect. In one form the shield interconnects are ground or power supply and the victim interconnect may be, for example, a clock signal or an RF signal. The number of shield interconnects and the number of protected victim interconnects varies depending upon design requirements. Either wire bonding or other interconnect technology (e.g. bump) is applicable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.