Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency
US6934199B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2002 |
| Grant date | Aug 23, 2005 |
| Priority date | — |
| Expiry date | Jun 25, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low write latency mode. The logic circuit receives a first signal indicative of whether the high-power, low write latency mode has been enabled, a second signal indicative of whether a row of memory cells in the memory device is active, a third signal indicative of whether the memory device is being operated in a power down mode, and a fourth signal indicative of whether read transmitters in the memory device are active. The logic circuit maintains power to the write receivers whenever the high-power, low write latency mode has been enabled if a row of memory cells in the memory device is active, the memory device is not being operated in the power down mode, and the read transmitters in the memory device are not active.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.