Semiconductor method and structure for simultaneously forming a trench capacitor dielectric and trench sidewall device dielectric
US6936512B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2002 |
| Grant date | Aug 30, 2005 |
| Priority date | — |
| Expiry date | Sep 27, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/0385
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a method, in an integrated, of forming a high-K node dielectric of a trench capacitor and a trench sidewall device dielectric at the same time. The method includes forming a trench in a single crystal layer of a semiconductor substrate, and forming an isolation collar along a portion of the trench sidewall, wherein the collar has a top below the top of the trench in the single crystal layer. Then, at the same time, a high-K dielectric is formed along the trench sidewall, the high-K dielectric extending in both an upper portion of the trench including above the isolation collar and in a lower portion of the trench below the isolation collar. The top of the isolation collar is then etched back to expose a portion of the single crystal substrate along the sidewall, and then, a node electrode is formed in conductive contact with the exposed sidewall and also in contact with the high-K dielectric in the lower portion, such that the high-K dielectric remains as a trench sidewall dielectric in the upper portion of the sidewall. In a DRAM memory cell structure, the trench sidewall dielectric may then be used as a gate dielectric of a vertical transistor which accesses t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.