Two-stage annealing method for manufacturing semiconductor substrates
US6936523B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 10, 2003 |
| Grant date | Aug 30, 2005 |
| Priority date | — |
| Expiry date | Feb 26, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76254
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a method for manufacturing a heterogeneous material structure. The method includes forming a predetermined detachment area in a source substrate, and bonding the source substrate to a handle substrate to form a source-handle structure. The source-handle-structure is then annealed at a first energy level that is lower than the energy of a thermal detachment budget and stopping before detachment of the source substrate. Lastly, the source-handle-structure is annealed at a second energy level that is lower than the first energy level at least until the substrate detaches at the predetermined detachment area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.