Integrated circuit with test pad structure and method of testing

US6937047B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Tu-Anh N. Tran · Austin, US
• Richard K. Eguchi · Austin, US
• Peter R. Harper · معلمی نژاد, US
• Chu-Chung Lee · Round Rock, US
• William Williams, III · Ipswich, US
• Lois Yong · Austin, US

Key dates

• Filing date: Aug 5, 2003
• Grant date: Aug 30, 2005
• Expiry date: Dec 2, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2224/05554
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A semiconductor device has a large number of bond pads on the periphery for wirebonding. The semiconductor device has a module as well as other circuitry, but the module takes significantly longer to test than the other circuitry. A relatively small number of the bond pads, the module bond pads, are required for the module testing due, at least in part, to the semiconductor device having a built-in self-test (BIST) circuitry. The functionality of these module bond pads is duplicated on the top surface of and in the interior of the semiconductor device with module test pads that are significantly larger than the bond pads on the periphery. Having large pads for testing allows longer probe needles, thus increasing parallel testing capability. Duplicating the functionality is achieved through a test pad interface so that the module bond pads and the module test pads do not have to be shorted together.