Memory device and method of storing fail addresses of a memory cell
US6937531B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 21, 2003 |
| Grant date | Aug 30, 2005 |
| Priority date | — |
| Expiry date | Aug 16, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The embodiments of the present invention are directed to a self-repair schema for memory chips, using a sortable fail-count/fail-address register. The embodiments of the present invention utilize the available redundancy efficiently by scanning the memory array to locate the n elements (WLs or CSLs) with the highest number of defects. A circuit preferably comprises one or more comparators to compare a fail count of an address in an input register with at least one fail count stored in the sortable fail-count/fail-address register. The embodiments of the present invention can be used for an on-chip redundancy calculation and can handle a two dimensional (i.e. row and column) redundancy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.