Method of fabricating semiconductor device having triple LDD structure and lower gate resistance formed with a single implant process
US6939770B1 · kind B1 · utility
2Cited by
7References
18Claims
0Family size
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Key dates
| Filing date | Jul 11, 2003 |
| Grant date | Sep 6, 2005 |
| Priority date | — |
| Expiry date | Jul 11, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0229
Abstract
A method of fabricating a semiconductor device having a triple LDD (lateral diffused dopants) structure is disclosed. This fabrication method requires a single implant process, leading to reduction in fabrication costs and fabrication time. Moreover, this fabrication method increases the surface area of the gate structure of the semiconductor device that is available for silicide to be formed, leading to lower gate resistance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.