Integrated circuit package and method of manufacturing the integrated circuit package
US6940154B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2002 |
| Grant date | Sep 6, 2005 |
| Priority date | — |
| Expiry date | Sep 15, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18301
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to an integrated circuit package and method of manufacturing an integrated circuit package. In one aspect, the present invention relates to an integrated circuit package including a lead frame having a lead with an inner pad and an outer pad connected by a connection member, wherein a region of the inner pad and a region of the outer pad are separated by a channel extending through a width of the lead. Such an integrated circuit package further includes a semiconductor die electrically coupled with the inner pad of the lead, and an encapsulant material encapsulating at least a portion of said lead frame, wherein a portion of said outer pad is exposed. In another aspect, the present invention relates to a method including providing a matrix of lead frames, each of the lead frames having a lead, forming a channel extending through a width of the lead to create an inner pad, an outer pad and a connection member in the lead, electrically coupling a semiconductor die with the inner pad, and encapsulating at least a portion of the lead frame such that at least a portion of the outer pad is exposed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.