High speed sense amplifier for memory output
US6940315B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2003 |
| Grant date | Sep 6, 2005 |
| Priority date | — |
| Expiry date | Mar 14, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sense amplifier circuit includes a latch circuit to enhance the speed of a sensing operation and to obviate the need for a latch circuit to capture the output value of the sense amplifier circuit. In one embodiment, first and second differential amplifiers provide a differential signal to the latch circuit. The high gain in the latch circuit resolves the differential signal to a logic signal, which is then provided to an output amplifier. In one embodiment, the differential signal is provided to the latch circuit after the differential signal across the input terminals of the first and second differential amplifiers exceeds a predetermined value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.