System and method for reducing leakage in memory cells using wordline control
US6940778B2 · kind B2 · utility
1Cited by
3References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2003 |
| Grant date | Sep 6, 2005 |
| Priority date | — |
| Expiry date | Mar 19, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment of the invention provides a circuit for reducing power in memory cells. The input of the circuit is connected to the wordline of the memory cells. When the wordline is active, the output of the circuit applies a voltage near VDD to the positive voltage supply node of the memory cells. When the wordline is inactive, the output of the circuit applies a voltage that is reduced by at least one Vt from VDD to the positive voltage supply node of the memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.