Integration scheme for metal gap fill, with fixed abrasive CMP

US6943114B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Peter Wrschka · Phoenix, US
• Werner Robl · Regensburg, DE
• Thomas Goebel · Wolfsberg, AT

Key dates

• Filing date: Feb 28, 2002
• Grant date: Sep 13, 2005
• Expiry date: Feb 28, 2022

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/959
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In a method of planarizing a semiconductor wafer, the improvement comprising polishing above metal interconnect lines to uniformly polish the topography of the wafer to a predetermined endpoint on the wafer sufficiently close above the metal interconnect lines, yet far enough away from the lines to prevent damage to the lines, comprising:a) filling gaps between metal interconnect lines of an inter metal dielectric in a wafer being formed, by depositing HDP fill on top of the metal interconnects, between the metal interconnects, and on the surface of a dielectric layer between the metal interconnects to create an HDP overfill;b) contacting the surface of HDP overfill of the processed semiconductor wafer from step a) with a fixed abrasive polishing pad; andc) relatively moving the wafer and the fixed abrasive polishing pad to affect a polishing rate sufficient to reach a predetermined endpoint and uniformly planar surface on the wafer sufficiently close above the metal interconnect lines and yet far enough away from the lines to prevent damage to the lines.