Electro-static discharge protection circuit and method for making the same
US6943396B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 17, 2003 |
| Grant date | Sep 13, 2005 |
| Priority date | — |
| Expiry date | Aug 5, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/395
Abstract
As disclosed herein, an electrostatic discharge (ESD) protection circuit is provided for an integrated circuit including a semiconductor substrate. The ESD protection circuit includes a plurality of active devices formed in the semiconductor substrate, the active devices being formed by a process including a plurality of steps carried out to form, at the same time, a plurality of active devices having a function other than ESD protection. For example, the ESD circuit may include an array of vertical transistors formed according to a process including many of the steps used to form, at the same time, vertical transistors of a DRAM array. Also disclosed is the formation of an ESD circuit in an “unusable” area of a semiconductor chip, such as under a bond pad, land or under bump metallization of the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.