Via construction for structural support
US6943446B2 · kind B2 · utility
1Cited by
4References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2002 |
| Grant date | Sep 13, 2005 |
| Priority date | — |
| Expiry date | Dec 16, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01019
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit having electrically conductive vias with a diameter of between about one micron and about fifty microns. Prior art vias have a diameter of between no less than 0.3 microns to no more than 0.8 microns. In this manner, stresses such as those that press down upon the top surface of the integrated circuit can be absorbed by the large vias and transferred past fragile layers, such as low k layers, so that the fragile layers are not damaged by the stresses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.