Method and apparatus for achieving higher product yields by using fractional portions of imbedded memory arrays
US6944807B2 · kind B2 · utility
1Cited by
1References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2002 |
| Grant date | Sep 13, 2005 |
| Priority date | — |
| Expiry date | Aug 24, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides a circuit and method for obtaining a fully functional microprocessor using only a fraction of the available on-chip cache. The memory sub-arrays of the on-chip cache are tested to determine which sub-arrays are functional. After determining which sub-arrays are functional, a set of sub-arrays is selected that constitute a binary fraction of the cache. The CPU is initialized to accommodate a smaller address space corresponding to the size of the selected sub-arrays. Finally, a group of signals are programmed to allow the CPU access to the selected sub-arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.