Method for manufacturing a single electron memory device having quantum dots between gate electrode and single electron storage element
US6946346B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2003 |
| Grant date | Sep 20, 2005 |
| Priority date | — |
| Expiry date | Dec 22, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/08
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
In a method for manufacturing a single electron memory device including a single electron storage element in a gate lamination pattern formed on a nano-scale channel region of a MOSFET, formation of the gate lamination pattern includes sequentially forming a lower layer and a single electron storage medium for storing a single electron tunneling through the lower layer on a substrate, forming an upper layer including a plurality of quantum dots on the single electron storage medium, forming a gate electrode layer on the upper layer to be in contact with the plurality of quantum dots, and patterning the lower layer, the single electron storage medium, the upper layer, and the gate electrode layer, in reverse order.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.