LDMOS transistor structure for improving hot carrier reliability

US6946706B1 · kind B1 · utility

Assignee

• NATIONAL SEMICONDUCTOR CORPORATION · US

Inventors

• Douglas Brisbin · San Jose, US
• David Tsuei · Sunnyvale, US
• Alexander H. Owens · Los Gatos, US
• Andy Strachan · Santa Clara, US

Key dates

• Filing date: Jul 9, 2003
• Grant date: Sep 20, 2005
• Expiry date: Jul 21, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/519

Abstract

An LDMOS structure which provides for reduced hot carrier effects. The reduction in hot carrier effects is achieved by increasing the size of the drain region of the LDMOS relative to the size of the source region. The larger size of the drain region reduces the concentration of electrons entering the drain region. This reduction in the concentration of electrons reduces the number of impact ionizations, which in turn reduces the hot carrier effects. The overall performance of the LDMOS is improved by reducing the hot carrier effects.