Electroplated interconnection structures on integrated circuit chips

US6946716B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Panayotis Andricacos · Ossining, US
• Harikilia Deligianni · Tenafly, US
• John O. Dukovic · Pleasantville, US
• Daniel C. Edelstein · White Plains, US
• Wilma Jean Horkans · Ossining, US
• Chao-Kun Hu · Somers, US
• Jeffrey Louis Hurd · Marlboro, US
• Kenneth P. Rodbell · Sandy Hook, US
• Cyprian Emeka Uzoh · San Jose, US
• Kwong Hon Wong · Wappingers Falls, US

Key dates

• Filing date: Feb 9, 2004
• Grant date: Sep 20, 2005
• Expiry date: Feb 9, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76885
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of CU electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.