Side-wall barrier structure and method of fabrication

US6946735B2 · kind B2 · utility

Assignee

• Infineon Inc. · DE

Inventors

• Stefan Gernhardt · Yokohama, JP
• Jenny Lian · Oshima, JP
• Andreas Hilliger · Yokohama, JP
• Rainer Bruchhaus · Yokohama, JP
• Uwe Wellhausen · Dresden, DE
• Nicolas Nagel · Yokohama, JP

Key dates

• Filing date: Nov 29, 2002
• Grant date: Sep 20, 2005
• Expiry date: Jul 11, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/692
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The invention includes a wafer having a poly silicon plug passing through a CP-contact. The poly silicon plug is formed from a relatively heavily doped poly silicon layer and a relatively lightly doped poly silicon layer. The relatively lightly doped poly silicon layer passes through the relatively heavily doped poly silicon layer to extend beyond the relatively heavily doped poly silicon layer towards the surface of the wafer. A barrier layer covers top and side walls of the relatively lightly doped poly silicon layer for reducing oxidation at the surface of the poly silicon plug. The wafer is fabricated by depositing a relatively heavily doped poly silicon layer in a CP-contact, depositing a relatively lightly doped poly silicon layer to pass through the relatively heavily doped poly silicon layer, and depositing a barrier layer to cover top and side walls of the relatively lightly doped poly silicon layer to reduce oxidation at the surface of the poly silicon plug.