Method of evaluating core based system-on-a-chip (SoC) and structure of SoC incorporating same
US6948105B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 12, 2001 |
| Grant date | Sep 20, 2005 |
| Priority date | — |
| Expiry date | Aug 11, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of debugging an individual core in core based system-on-a-chip (SOC) ICs with high accuracy and observability, and a structure of SOC incorporating the method. The method includes the steps of building two or more metal layers of a pad frame for each core in an SoC while connecting I/O (input and output) pads on a lower metal layer to a top metal layer, thereby exposing all I/O pads and power pads on a surface of the top metal layer of the pad frame of each core, and applying test vector to each core through the I/O pads on the top metal layer of the core and evaluating response outputs of the core received through the I/O pads on the top metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.