Line edge roughness reduction for trench etch
US6949460B2 · kind B2 · utility
13Cited by
6References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2003 |
| Grant date | Sep 27, 2005 |
| Priority date | — |
| Expiry date | Nov 12, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76802
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for etching a trench to a trench depth in a dielectric layer over a substrate is provided. An ARC is applied over the dielectric layer. A photoresist mask is formed on the ARC, where the photoresist mask has a thickness. The ARC is etched through. A trench is etched into the dielectric layer with a dielectric to photoresist etch selectivity between 1:1 and 2:1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.