Integrated circuit multiplexer including transistors of more than one oxide thickness
US6949951B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2004 |
| Grant date | Sep 27, 2005 |
| Priority date | — |
| Expiry date | Jun 15, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1778
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multiplexer that can be used, for example, in a programmable logic device (PLD). The multiplexer includes a plurality of pass transistors passing a selected one of several input values to an internal node, which drives a buffer that provides the multiplexer output signal. The pass transistors can be controlled, for example, by values stored in memory cells of a PLD. The pass transistors have a first oxide thickness and are controlled by a value having a first operating voltage. The buffer includes transistors having a second and thinner oxide thickness, and is operated at a second and lower operating voltage. Where memory cells are used to control the pass transistors, the memory cells include transistors having the first oxide thickness and operate at the first operating voltage. Some embodiments also include transistors of varying gate length for each of the pass transistors, buffer transistors, and memory cell transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.