Imprint suppression circuit scheme
US6950328B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2003 |
| Grant date | Sep 27, 2005 |
| Priority date | — |
| Expiry date | Dec 11, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ferroelectric memory array includes a plurality of memory pages each formed of a plurality of ferroelectric memory cells. The ferroelectric memory cells are supplied by common word lines. Status memory cells are connected to each of the plurality of memory pages, each status memory cell stores the status of the memory page to which it is connected. A plurality of sense amplifiers each receives inputs from a pair of bit lines. Each of the bit lines receives inputs from the ferroelectric memory cells of a plurality of the memory pages. The sense amplifiers write back data into the memory cells and status cells in reversed states following read operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.