System and method to screen defect related reliability failures in CMOS SRAMS
US6950355B2 · kind B2 · utility
2Cited by
17References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2001 |
| Grant date | Sep 27, 2005 |
| Priority date | — |
| Expiry date | Dec 18, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for testing a semiconductor wafer. An array of probes is coupled to the semiconductor wafer. Then a voltage difference is applied across a plurality of adjacent metal line pairs (e.g., wordline and/or bitline pairs) of one or more SRAM arrays of at least one die. Application of the voltage difference induces failure of metal stringers or defects between the adjacent lines. Additionally, the voltage can be applied across respective pairs of substantially all parallel metal lines of the one or more SRAM arrays of more that one die of the semiconductor wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.