Phase splitter using digital delay locked loops
US6950487B2 · kind B2 · utility
30Cited by
9References
56Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 18, 2001 |
| Grant date | Sep 27, 2005 |
| Priority date | — |
| Expiry date | Sep 27, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/089
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase splitter using digital delay locked loop (DLL) to receive complementary input clock signals to generate a plurality of output signals having different phase shifts. When the DLL is locked, the delay resolution of the phase splitter is equal to two delay stages of the DLL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.