Integrated circuit with timing adjustment mechanism and method
US6950956B2 · kind B2 · utility
132Cited by
68References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2003 |
| Grant date | Sep 27, 2005 |
| Priority date | — |
| Expiry date | Nov 19, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device includes a receiver, a register and a clock circuit. The receiver samples data from an external signal line in response to an internal clock signal. The register stores a value that represents a timing offset to adjust the time at which the data is sampled. The clock circuit generates the internal clock signal such that the internal clock signal maintains a controlled timing relationship with respect to an external clock signal. The clock circuit includes an interpolator that phase mixes a set of reference clock signals such that the internal clock signal is phase offset in accordance with the value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.