Place-and-route with power analysis
US6950998B1 · kind B1 · utility
31Cited by
2References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 22, 2003 |
| Grant date | Sep 27, 2005 |
| Priority date | — |
| Expiry date | Jun 17, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for placing and routing an electronic circuit design. Various embodiments are disclosed for analyzing placed and/or routed designs for power consumption characteristics and timing characteristics. New designs are iteratively generated in order to reduce power consumption and satisfy timing requirements of the design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.