Tim Tuan
49Patents
14h-index
49Co-inventors
81Inventor score
Filing activity: Apr 22, 2003 → Nov 14, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7973556B1 | System and method for using reconfiguration ports for power management in integrated circuits | Electricity | 75 | Active |
| US7098689B1 | Disabling unused/inactive resources in programmable logic devices for static power reduction | Electricity | 51 | Expired |
| US7581124B1 | Method and mechanism for controlling power consumption of an integrated circuit | Physics | 34 | Active |
| US7498835B1 | Implementation of low power standby modes for integrated circuits | Emerging Cross-Sectional Technologies | 31 | Expired |
| US6950998B1 | Place-and-route with power analysis | Physics | 31 | Expired |
| US7620926B1 | Methods and structures for flexible power management in integrated circuits | Electricity | 27 | Active |
| US7764081B1 | Programmable logic device (PLD) with memory refresh based on single event upset (SEU) occurrence to maintain soft error immunity | Electricity | 26 | Active |
| US7498836B1 | Programmable low power modes for embedded memory blocks | Electricity | 23 | Expired |
| US7504854B1 | Regulating unused/inactive resources in programmable logic devices for static power reduction | Electricity | 18 | Active |
| US7477073B1 | Structures and methods for heterogeneous low power programmable logic device | Electricity | 17 | Active |
| US10866753B2 | Data processing engine arrangement in a device | Physics | 15 | Active |
| US7490302B1 | Power gating various number of resources based on utilization levels | Physics | 15 | Active |
| US7549139B1 | Tuning programmable logic devices for low-power design implementation | Electricity | 14 | Expired |
| US8159263B1 | Programmable integrated circuit with voltage domains | Electricity | 14 | Active |
| US7992020B1 | Power management with packaged multi-die integrated circuit | Emerging Cross-Sectional Technologies | 12 | Active |
| US11336287B1 | Data processing engine array architecture with memory tiles | Electricity | 12 | Active |
| US7810058B1 | Early power estimator for integrated circuits | Physics | 11 | Expired |
| US7243312B1 | Method and apparatus for power optimization during an integrated circuit design process | Physics | 11 | Expired |
| US7417454B1 | Low-swing interconnections for field programmable gate arrays | Electricity | 9 | Expired |
| US7545177B1 | Method and apparatus for leakage current reduction | Electricity | 9 | Active |
| US7562332B1 | Disabling unused/inactive resources in programmable logic devices for static power reduction | Electricity | 9 | Active |
| US10635622B2 | System-on-chip interface architecture | Physics | 6 | Active |
| US11520717B1 | Memory tiles in data processing engine array | Physics | 6 | Active |
| US9348959B1 | Optimizing supply voltage and threshold voltage | Emerging Cross-Sectional Technologies | 6 | Active |
| US7253661B1 | Method and apparatus for a configurable latch | Electricity | 5 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.