Method for forming inside nitride spacer for deep trench device DRAM cell
US6951822B2 · kind B2 · utility
35Cited by
3References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 28, 2001 |
| Grant date | Oct 4, 2005 |
| Priority date | — |
| Expiry date | May 26, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/0385
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for forming an inside nitride spacer in a deep trench device DRAM cell. The method includes etching a stud from a semiconductor material including a first spacer positioned on the sidewalls of the deep trench, wherein two of the sidewalls are formed of isolation trench oxide. The method further includes depositing an oxide layer on the surface of the semiconductor, and depositing a second spacer in the deep trench of the semiconductor, wherein the second spacer has a positive taper relative to the isolation trench oxide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.