Semiconductor memory array of floating gate memory cells with buried bit-line and raised source line
US6952033B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2002 |
| Grant date | Oct 4, 2005 |
| Priority date | — |
| Expiry date | Apr 2, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0425
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A self aligned method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The drain region is formed underneath the trench, and the channel region includes a first portion that extends vertically along a sidewall of the trench and a second portion that extends horizontally along the substrate surface. An electrically conductive floating gate is formed over and insulated from a portion of the channel region. A raised source line of conductive material is disposed over the source region, and laterally adjacent to and insulated from the floating gate. An electrically conductive control gate is formed having a first portion disposed in the trench and a second portion formed over but insulated from the floating gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.