ESD protection snapback structure for overvoltage self-protecting I/O cells

US6952039B1 · kind B1 · utility

Assignee

• NATIONAL SEMICONDUCTOR CORPORATION · US

Inventors

• Vladislav Vashchenko · Palo Alto, US
• Ann Concannon · San Jose, US
• Peter J. Hopper · San Jose, US
• Marcel ter Beek · Pleasanton, US

Key dates

• Filing date: Sep 4, 2003
• Grant date: Oct 4, 2005
• Expiry date: Sep 4, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/603

Abstract

In a self protection I/O, a multiple gate NMOS structure is designed to shift the avalanche multiplication region away from the edge of the gate nearest the drain. This is achieved by providing a lightly doped region between the edge of the gate and the ballast region of the drain.