Design analysis tool for path extraction and false path identification and method thereof

US6952812B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Magdy S. Abadir · Austin, US
• Jing Zeng · Shanghai, CN
• Jayanta Bhadra · Austin, US

Key dates

• Filing date: Feb 13, 2001
• Grant date: Oct 4, 2005
• Expiry date: Sep 20, 2022

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318328
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A design analysis tool performs path extraction translation and false path identification functions. The design analysis tool is utilized with a conventional automated test pattern generator and timing analysis tools. By checking for four specific criteria, a fast and efficient way to detect whether a circuit path is false or active is accomplished. A final value condition is checked and, if that test is met, a side value propagation condition is checked. Assuming both tests result in the path still being active, the test is terminated. If the side value propagation conditions are not satisfied, then an initial value condition and a slower path condition is checked. The checks are made to determine whether or not conditions exist in the path that makes the path false. The information may be obtained quickly from the timing analysis information and the result of the ATPG tool.