Process for fabrication of nitride layer with reduced hydrogen content in ONO structure in semiconductor device
US6955965B1 · kind B1 · utility
14Cited by
21References
20Claims
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Key dates
| Filing date | Dec 9, 2003 |
| Grant date | Oct 18, 2005 |
| Priority date | — |
| Expiry date | Mar 10, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Process for fabricating a charge trapping dielectric flash memory device including steps of providing a semiconductor substrate; forming on the semiconductor substrate a bottom oxide layer; depositing on the bottom oxide layer a nitride layer, the deposited nitride layer having a first hydrogen content; and applying a treatment to reduce the first hydrogen content to a second hydrogen content.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.