Integrated semiconductor memory with wordlines conductively connected to one another in pairs

US6956260B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Dirk Manger · Dresden, DE
• Till Schlosser · Dresden, DE
• Martin Popp · Dresden, DE
• Michael Sesterhenn · Dresden, DE

Key dates

• Filing date: Jun 17, 2003
• Grant date: Oct 18, 2005
• Expiry date: Jun 17, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/488

Abstract

In semiconductor memories, in particular DRAMs, the memory cells of which have vertical transistors at vertical lands formed from substrate material, gate electrodes are formed as spacers which run around the land. The gate electrodes of adjacent memory cells conventionally have to be retroactively connected to form word lines. It is known to fill spaces between adjacent lands with an oxide, with the result that the spacers are formed directly as word lines but only cover two side walls of a land. Two transistors which are connected in parallel are formed at these side walls instead of a single transistor, since the gate electrode does not run around the land. The invention proposes a method for fabricating a semiconductor memory in which all four side walls of a land are covered by the word lines and at the same time lands of adjacent memory cells are connected to one another by the word lines.