Leakage current reduction method
US6956398B1 · kind B1 · utility
1Cited by
1References
8Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 23, 2004 |
| Grant date | Oct 18, 2005 |
| Priority date | — |
| Expiry date | Apr 8, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0016
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The method for powering down a circuit for a data retention mode includes: changing a supply voltage node from an active power voltage level to an inactive power level; coupling a source of a P channel device to the supply voltage node; providing a retaining power supply voltage level to a back gate of the P channel device; changing a drain voltage of the P channel device to a reference voltage level, wherein the reference voltage level is different from the retaining power supply voltage level; and changing a gate voltage of the P channel device to the reference voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.