Data streaming mechanism in a microprocessor
US6957305B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2002 |
| Grant date | Oct 18, 2005 |
| Priority date | — |
| Expiry date | Oct 8, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention provides a dual usage cache reload buffer (CRB) to hold both demand loads as well as prefetch loads. A new form of a data cache block touch (DCBT) instruction specifies which level of the cache hierarchy to prefetch data into. A first asynchronous form of a DCBT instruction is issued to prefetch a stream of data into a L2 cache. A second synchronous form of a DCBT instruction is used to prefetch data from the L2 cache to the CRB in the main CPU, which will bypass the L1 data cache and forward data directly to the register file. This CRB has a dual usage and is used to hold both normal cache reloads as well as the aforementioned prefetched cache lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.