Memory device with reduced cell size

US6958269B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Josef Czeslaw Mitros · Richardson, US
• Imran Khan · Richardson, US
• Lily Springer · Dallas, US

Key dates

• Filing date: Jun 24, 2002
• Grant date: Oct 25, 2005
• Expiry date: Jun 24, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/035

Abstract

A method for manufacturing a memory device includes forming an oxide layer adjacent a substrate. A floating gate layer is formed and disposed outwardly from the oxide layer. A dielectric layer is formed, such that it is disposed outwardly from the floating gate layer. Then, a conductive material layer is formed and disposed outwardly from the dielectric layer, wherein the conductive material layer forms a control gate that is substantially isolated from the floating gate layer by the dielectric layer.