Self-aligned method of forming a semiconductor memory array of floating gate memory cells with buried floating gate, pointed floating gate and pointed channel region, and a memory array made thereby
US6958273B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2003 |
| Grant date | Oct 25, 2005 |
| Priority date | — |
| Expiry date | Jun 11, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A method of forming a floating gate memory cell array, and the array formed thereby, wherein a trench is formed into the surface of a semiconductor substrate. The source and drain regions are formed underneath the trench and along the substrate surface, respectively, with a non-linear channel region therebetween. The floating gate has a lower portion disposed in the trench and an upper portion disposed above the substrate surface and having a lateral protrusion extending parallel to the substrate surface. The lateral protrusion is formed by etching a cavity into an exposed end of a sacrificial layer and filling it with polysilicon. The control gate is formed about the lateral protrusion and is insulated therefrom. The trench sidewall meets the substrate surface at an acute angle to form a sharp edge that points toward the floating gate and in a direction opposite to that of the lateral protrusion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.