Shallow trench isolation structure
US6958521B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2003 |
| Grant date | Oct 25, 2005 |
| Priority date | — |
| Expiry date | Aug 11, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Method for preventing sneakage in shallow trench isolation and STI structure thereof. A semiconductor substrate having a pad layer and a trench formed thereon is provided, followed by the formation of a doped first lining layer on the sidewall of the trench. A second lining layer is then formed on the doped first lining layer. Etching is then performed to remove parts of the first lining layer and the second lining layer so that the height of the first lining layer is lower than the second lining layer. A sacrificial layer is then formed on the pad layer and filling the trench. Diffusion is then carried out so that the doped ions in the first lining layer out-diffuse to the substrate and form diffuse regions outside the two bottom corners of the trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.