Method of fabricating three dimensional gate structure using oxygen diffusion
US6960509B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2004 |
| Grant date | Nov 1, 2005 |
| Priority date | — |
| Expiry date | Jun 30, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02274
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method of fabricating a silicon fin useful in preparing FinFET type semiconductor structures. The method is particularly useful for creating fins with a width and smoothness appropriate for sub-50 nm type gates. The method begins with a silicon fin prepared by lithographic means from an SOI type structure such that the fin is larger in dimension, particularly width, than is desired in the final fin. If desired the silicon fin can include a nitride cap. A conformal diffusion layer, such as of silicon dioxide, is then deposited onto the fin and silicon dioxide substrate. A PECVD deposition using TEOS gas is one method to deposit the diffusion layer. The coated fin is then heated and exposed to oxygen. The oxygen diffuses through the diffusion layer and converts a portion of the silicon material to silicon dioxide. This oxidation continues until a desired amount of silicon material is converted to SiO2 such that the remaining silicon has the desired dimensions. The silicon fin is then exposed through wet etching steps that remove the silicon dioxide coating.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.