Recording test information to identify memory cell errors
US6961880B2 · kind B2 · utility
3Cited by
4References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 30, 2001 |
| Grant date | Nov 1, 2005 |
| Priority date | — |
| Expiry date | Aug 23, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5606
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of recording test information to identify a location of errors in Integrated Circuits (ICs) includes scanning a plurality of ICs with an input signal, each IC having a plurality of data locations and comparing an output response at each data location with an expected value for the data location. The method also includes storing an address in a buffer for each data location where the response at the data location does not equal the expected value corresponding to the data location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.