Integrated circuit insulator and method
US6962883B2 · kind B2 · utility
2Cited by
4References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 5, 2003 |
| Grant date | Nov 8, 2005 |
| Priority date | — |
| Expiry date | Nov 10, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02274
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A two-stage plasma enhance dielectric deposition with a first stage of low capacitively-coupled RF bias with conformal deposition (202) followed by high capacitively-coupled RF bias for planarizing deposition (204) limits the charge build up on the underlying structure (104, 106, 108).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.